TM 1–1520–238–T–3
9–6
9–20 SIGNAL NAME:
LH FAB MRTU TYPE I INPUT BIT STATUS
MEMORY LOCATION: 001062
MEMORY DATA BIT(S):
14
(BINARY)
CONDITION:
(None)
SIGNAL FUNCTION:
Indicates status of turn–on test of input circuitry.
REMARKS: From LH FAB MRTU Type I to FCC.
PASS:
If second digit on HOD is 7, go to paragraph 9–21.
FAIL: Location of fault: MUX FAB L circuit breaker, wiring from MUX FAB L circuit breaker to LH FAB
MRTU Type I, LH FAB MRTU Type I. Troubleshoot wiring to isolate fault
(TM 9–1230–476–20–2).
9–21 SIGNAL NAME:
LH FAB MRTU TYPE I AD BIT STATUS
MEMORY LOCATION: 001062
MEMORY DATA BIT(S):
13
(BINARY)
CONDITION:
(None)
SIGNAL FUNCTION:
Indicates self–test status of analog to digital converter.
REMARKS: From LH FAB MRTU Type I to FCC.
PASS:
If third digit on HOD is 1, go to paragraph 9–22.
FAIL: Location of fault: MUX FAB L circuit breaker, wiring from MUX FAB L circuit breaker to LH FAB
MRTU Type I, LH FAB MRTU Type I. Troubleshoot wiring to isolate fault
(TM 9–1230–476–20–2).
9–22 SIGNAL NAME:
LH FAB MRTU TYPE I SERIAL DIGITAL ERROR
MEMORY LOCATION: 001062
MEMORY DATA BIT(S):
10
(BINARY)
CONDITION:
(None)
SIGNAL FUNCTION:
Monitors target acquisition designation sight (TADS).
REMARKS: From LH FAB MRTU Type I to FCC.
PASS:
Location of fault if fourth digit on HOD is 0: replace FCC (TM 9–1230–476–20–1).
FAIL: Location of fault: go to Chapter 15, paragraph 15–27.
9–23 SIGNAL NAME:
LH FAB MRTU TYPE I SERIAL DIGITAL ERROR
MEMORY LOCATION: 001124
MEMORY DATA BIT(S):
10
(BINARY)
CONDITION:
(None)
SIGNAL FUNCTION:
Monitors rounds counter controller.
REMARKS: From LH FAB MRTU Type I to FCC.
PASS:
If fourth digit on HOD is 0, go to paragraph 9–24.
FAIL: Location of fault: go to Chapter 5, paragraph 5–8.
9–24 SIGNAL NAME:
LH FAB MRTU TYPE I SERIAL DIGITAL ERROR
MEMORY LOCATION: 001157
MEMORY DATA BIT(S):
10
(BINARY)
CONDITION:
(None)
SIGNAL FUNCTION:
Monitors rounds counter controller.
REMARKS: From LH FAB MRTU Type I to FCC.
PASS:
If fourth digit on HOD is 0, go to paragraph 9–25.
FAIL: Location of fault: go to Chapter 5, paragraph 5–8.
